Data communications systems, and in general many other types of electronic systems, rely on a backplane based architecture comprising a plurality of circuit cards that plug into, or are otherwise electrically connected to, a system backplane. The system backplane is a facility over which the circuit cards can communicate with each other and over which power is supplied to the circuit cards. Examples of the type circuit cards included in data communications systems include control cards, input/output (I/O) cards, line cards, and processor cards.
A typical data communication system employs multiple serial links across the backplane for communications between the various circuit cards of the system. Generally, such communications occur over bidirectional serial links, each of which comprises a pair of unidirectional links each link of the pair being for data transmission in an opposite direction than the other link of the pair. A serial input/output (I/O) interface at each end of each bidirectional link comprises a transmitter and receiver. Typically both the transmitter and the receiver are implemented in one component known as a serializer/deserializer (SERDES). Generally, on any given unidirectional serial link, the transmitter at one end of the link is asynchronous to the receiver at the other end of that link. This is because transmitter and receiver each derive their timing from a respective reference clock, and those reference clocks are asynchronous to each other since they are typically generated locally at a respective circuit card.
A method exists to compensate for timing discrepancies in clocking of the transmitter and receiver at either end of a unidirectional serial link, but this method requires the use of clocks with known accuracies, which tends to make it costly to implement. Also, a requirement of the method is that the transmitter sends several special timing characters, known as idle or ‘stuff’ characters, every predetermined interval of time so that the receiver can compensate for its receive buffer fill rate. Since the interval between the transmission of the special timing characters is fixed, as well as the number of special characters that are inserted, the accuracy required by a reference clock used by the method is dictated by this interval and sequence length of the special timing characters. This aspect of the method hinders the use of inexpensive clocking sources in systems employing the method. Furthermore, in-band insertion of idle characters for the unique purpose of timing compensation at the receiver consumes link bandwidth as overhead, and is therefore inefficient.
In view of the foregoing, it would be desirable to have a solution that allows more design freedom in the selection of serial link reference clock sources than is available using the aforementioned known timing compensation method.